Home > Products > Transceivers > CLR-QSFP-SR4                 CLR-QSFP-SR4       40GBase-SR4 QSFP+ Optical Transceiver Module, MPO   Multimode, 850nm, 300m                       Specifications                   Absolute Maximum Ratings Parameter Symbol Min Typical Max Unit Supply Voltage Vcc -0,3 3,6 V Input Voltage Vin -0,3 Vcc+0.3 V Storage Temperature Tst -20 85 ºC Case Operating Temperature Top 0 70 ºC Humidity(non-condensing) Rh 5 95 % xxxx Recommended Operating Conditions Parameter Symbol Min Typical Max Unit Supply Voltage Vcc 3,13 3,3 3,47 V Operating Case temperature Tca 0 70 ºC Data Rate Per Lane fd 10,3 10,5 Gbps Humidity Rh 5 85 % Power Dissipation Pm 1,5 W   Electrical Specifications Parameter Symbol Min Typical Max Unit Differential input impedance Zin 90 100 110 ohm Differential Output impedance Zout 90 100 110 ohm Differential input voltage amplitude ΔVin 300 1100 mVp-p Differential output voltage amplitude ΔVout 500 800 mVp-p Skew Sw 300 ps Bit Error Rate BER E-12 Input Logic Level High VIH 02 VCC V Input Logic Level Low VIL 0 0,8 V Output Logic Level High VOH VCC-0.5 VCC V Output Logic Level Low VOL 0 0,4 V   Optical Characteristics Parameter Symbol Min Typical Max Unit Transmitter Centre Wavelength λc 840 850 860 nm RMS spectral width ∆λ - - 0,65 nm Average launch power, each lane Pout -6,5 - -1 dBm Difference in launch power between any two lanes (OMA) 4 dB Extinction Ratio ER 3 - - dB Peak power, each lane 4 dBm Transmitter and dispersion penalty (TDP), each lane TDP 3,5 dB Average launch power of OFF transmitter, each lane -30 dB Eye Mask coordinates: X1, X2, X3, Y1, Y2, Y3 SPECIFICATION VALUES 0.23, 0.34, 0.43, 0.27, 0.35, 0.4 Receiver Centre Wavelength λc 840 850 860 nm Stressed receiver sensitivity in OMA -5,4 dBm Maximum Average power at receiver , each lane 2,4 dBm Minimum Average power at receiver , each lane -9,5 dBm Receiver Reflectance -12 dB Peak power, each lane 4 dBm LOS Assert -30 dBm LOS De-Assert - OMA -7,5 dBm LOS Hysteresis 0,5 dB   Pin Descriptions Pin Logic Symbol Name/Description 1 GND Module Ground 2 CML-I Tx2- Transmitter inverted data input 3 CML-I Tx2+ Transmitter non-inverted data input 4 GND Module Ground 5 CML-I Tx4- Transmitter inverted data input 6 CML-I Tx4+ Transmitter non-inverted data input 7 GND Module Ground 8 LVTTL-I MODSEIL Module Select 9 LVTTL-I ResetL Module Reset 10 VCCRx +3.3v Receiver Power Supply 11 LVCMOS-I SCL 2-wire Serial interface clock 12 LVCMOS-I/O SDA 2-wire Serial interface data 13 GND Module Ground 14 CML-O RX3+ Receiver non-inverted data output 15 CML-O RX3- Receiver inverted data output 16 GND Module Ground 17 CML-O RX1+ Receiver non-inverted data output 18 CML-O RX1- Receiver inverted data output 19 GND Module Ground 20 GND Module Ground 21 CML-O RX2- Receiver inverted data output 22 CML-O RX2+ Receiver non-inverted data output 23 GND Module Ground 24 CML-O RX4- Receiver inverted data output 25 CML-O RX4+ Receiver non-inverted data output 26 GND Module Ground 27 LVTTL-O ModPrsL Module Present, internal pulled down to GND 28 LVTTL-O IntL Interrupt output, should be pulled up on host board 29 VCCTx +3.3v Transmitter Power Supply 30 VCC1 +3.3v Power Supply 31 LVTTL-I LPMode Low Power Mode 32 GND Module Ground 33 CML-I Tx3+ Transmitter non-inverted data input 34 CML-I Tx3- Transmitter inverted data input 35 GND Module Ground 36 CML-I Tx1+ Transmitter non-inverted data input 37 CML-I Tx1- Transmitter inverted data input 38 GND Module Ground   Timing for Soft Control and Status Functions Parameter Symbol Max Unit Conditions Initialization Time t_init 2000 ms Time from power on, hot plug or rising edge of Reset until the module is fully functional Reset Init Assert Time t_reset_init 2 μs A Reset is generated by a low level longer than the minimum reset pulse time present on the ResetL pin. Serial Bus Hardware Ready Time t_serial 2000 ms Time from power on until module responds to data transmission over the 2-wire serial bus Monitor Data Ready Time t_data 2000 ms Time from power on to data not ready, bit 0 of Byte 2, deasserted and IntL asserted Reset Assert Time t_reset 2000 ms Time from rising edge on the ResetL pin until the module is fully functional LPMode Assert Time ton_LPMode 100 μs Time from assertion of LPMode (Vin:LPMode = Vih) until module power consumption enters lower Power Level IntL Assert Time ton_IntL 200 ms Time from occurrence of condition triggering IntL until Vout:IntL = Vol IntL Deassert Time toff_IntL 500 μs Time from clear on read3 operation of associated flag until Vout:IntL = Voh. This includes deassert times for Rx LOS, Tx Fault and other flag bits. Rx LOS Assert Time ton_los 100 ms Time from Rx LOS state to Rx LOS bit set and IntL asserted Tx Fault Assert Time ton_Txfault 200 ms Time from Tx Fault state to Tx Fault bit set and IntL asserted Flag Assert Time ton_flag 200 ms Time from occurrence of condition triggering flag to associated flag bit set and IntL asserted Mask Assert Time ton_mask 100 ms Time from mask bit set until associated IntL assertion is inhibited Mask Deassert Time toff_mask 100 ms Time from mask bit cleared until associated IntlL operation resumes ModSelL Assert Time ton_ModSelL 100 μs Time from assertion of ModSelL until module responds to data transmission over the 2-wire serial bus ModSelL Deassert Time toff_ModSelL 100 μs Time from deassertion of ModSelL until the module does not respond to data transmission over the 2-wire serial bus Power_over-ride or Power-set Assert Time ton_Pdown 100 ms Time from P_Down bit set until module power consumption enters lower Power Level Power_over-ride or Power-set Deassert Time toff_Pdown 300 ms Time from P_Down bit cleared until the module is fully functional