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  CLR-HGS-SR4
   
  100GBase-SR4 QSFP28 Optical Transceiver Module
  Multimode, MPO, 100m
   
 
              
             
  Specifications  
             
 
Absolute Maximum Ratings
Parameter Symbol Min Typical Max Unit
Supply Voltage Vcc -0.3 3.6 V
Input Voltage Vin -0.3 Vcc+0.3 V
Storage Temperature Tst -20 85 ºC
Case Operating Temperature Top 0 70 ºC
Humidity (non-condensing) Rh 5 95 %
 
Recommended Operating Conditions
Parameter Symbol Min Typical Max Unit
Supply Voltage Vcc 3.13 3.3 3.47 V
Operating Case temperature Tca 0 70 ºC
Data Rate Per Lane fd   25.78125   Gbps
Humidity Rh 5 85 %
Power Dissipation Pdiss 2 2.5 W
Fiber Bend Radius Rb 3   cm
 
Electrical Specifications
Parameter Symbol Min Typical Max Unit
Power Consumption P     2.5 W
Differential input impedance Zin 90 100 110 Ohm
Differential output impedance Zout 90 100 110 Ohm
Differential input voltage amplitude ΔVin 300 1100 mVp-p
Differential output voltage amplitude ΔVout 500 800 mVp-p
Skew Sw     300 ps
Bit Error Rate BER   E-5    
Input Logic Level High VIH 2.0   Vcc V
Input Logic Level Low VIL 0   0.8 v
Output Logic Level High VOH Vcc-0.5   Vcc V
Output Logic Level Low VOL 0   0.4 V
 
Optical Characteristics
Parameter Symbol Min Typical Max Unit
Transmitter
Centre Wavelength λc 840 850 860 nm
RMS spectral width Δλ     0.6 nm
Average Launch Power per each Lane Pavg -8.4   2.4 dBm
Optical Modulation Amplitude OMA, each Lane Poma -6.4   3 dBm
Transmitter and dispersion eye closure (TDEC), each lane TDEC     4.3 dB
Extinction Ratio ER 3     dB
Average launch power of OFF transmitter, each lane Poff     -30 dB
Eye Mask coordinates: X1, X2, X3, Y1, Y2, Y3   SPECIFICATION VALUES {0.3,0.38,0.45,0.35,0.41.0.5}  
Receiver
Centre Wavelength λc 840 850 860 nm
Stressed Receiver Sensitivity in OMA -5.2 dBm
Maximum Average power at receiver, each lane   2.4 dBm
Minimum Average power at receiver, each lane   -10.3 dBm
Receiver Reflectance -12 dB
RX_ LOS_ Assert LOSA -30     dBm
RX_ LOS_ De-Assert LOSD   -7.5 dBm
RX_ LOS_ Hysteresis LOSH 0.5   dB
 
Pin Descriptions
Pin Logic Symbol Name/Description
1 GND Module Ground
2 CML-I Tx2- Transmitter inverted data input
3 CML-I Tx2+ Transmitter non-inverted data input
4 GND Module Ground
5 CML-I Tx4- Transmitter inverted data input
6 CML-I Tx4+ Transmitter non-inverted data input
7 GND Module Ground
8 LVTTL-I MODSEIL Module Select
9 LVTTL-I ResetL Module Reset
10 VCCRx +3.3v Receiver Power Supply
11 LVCMOS-I SCL 2-wire Serial interface clock
12 LVCMOS-I/O SDA 2-wire Serial interface data
13 GND Module Ground
14 CML-O RX3+ Receiver non-inverted data output
15 CML-O RX3- Receiver inverted data output
16 GND Module Ground
17 CML-O RX1+ Receiver non-inverted data output
18 CML-O RX1- Receiver inverted data output
19 GND Module Ground
20 GND Module Ground
21 CML-O RX2- Receiver inverted data output
22 CML-O RX2+ Receiver non-inverted data output
23 GND Module Ground
24 CML-O RX4- Receiver inverted data output
25 CML-O RX4+ Receiver non-inverted data output
26 GND Module Ground
27 LVTTL-O ModPrsL Module Present, internal pulled down to GND
28 LVTTL-O IntL Interrupt output, should be pulled up on host board
29 VCCTx +3.3v Transmitter Power Supply
30 VCC1 +3.3v Power Supply
31 LVTTL-I LPMode Low Power Mode
32 GND Module Ground
33 CML-I Tx3+ Transmitter non-inverted data input
34 CML-I Tx3- Transmitter inverted data input
35 GND Module Ground
36 CML-I Tx1+ Transmitter non-inverted data input
37 CML-I Tx1- Transmitter inverted data input
38 GND Module Ground
 
 
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  mechanical drawing